The increasing use of digital logic in circuit assemblies and the increasing complexity of these digital logic circuits has generated a search for test techniques other than the traditional "functional test" methods that apply digital patterns to the circuit assembly inputs and compare the response from the circuit assembly outputs to expected values. These functional test input signals may be complex and difficult to specify properly since they must cause digital circuit activity to propogate from the circuit assembly inputs through various digital devices to the site of a potential fault and further cause transmission of signals from the fault site to the assembly output. One alternative technique is known as "incircuit" testing. In this technique, one applies a digital pattern directly to the device under test, and detects the output from that device in order to verify proper operation. Early implementation of such a technique using a probe is described in the September 1972 issue of the Hewlett-Packard Journal in an article entitled "Logic Pulser and Probe: a New Digital Troubleshooting Team", By Robin Adler and Jan R. Holland. The implementation of such a technique is the subject of U.S. Pat. Nos. 3,543,154; 3,641,509; 3,670,235; 3,781,689; and 3,965,468.
Further developments have occurred in the class of test equipment using this test technique. These developments include the ability to pulse more than one node or device at one time, the ability to pulse larger numbers of patterns in order to test more complex devices, the ability to handle third state data and others. Such equipment is manufactured by GenRad, Inc., Concord, Mass. The implementation of such techniques are described in U.S. Pat. Nos. 3,870,953; 4,236,246.
The implementation of the "incircuit" test technique requires application of a pattern directly to the device under test and measurement of the response from the device. Since digital logic circuits, except those at the input or output of the circuit assembly, are generally connected to other digital logic circuits, the application of the pattern requires overdriving the pattern which is applied by the "upstream" logic devices during normal device operation. Upstream logic devices are those devices whose outputs drive the inputs of the device under test.
FIG. 1 represents a prior art design. Prior art techniques of pattern application involve taking a file of generic patterns for a specific device, combining it with a topological description of the board, and applying these patterns device by device to the board under test. The design is capable of providing a sequence of patterns to the device under test for suitable periods long enough to test the individual device. Between each test, there is a delay caused by automatic tester overhead and used for the protection of devices. These fixed periods of time permit devices upstream to cool. However, several problems are apparent. First, the fixed time period between tests, unrelated to the actual time necessary for the devices upstream to cool, reduces throughput. Second, in order to test certain complex logic devices, it is necessary to first place these devices into a known state before beginning the test. This process, known as "homing", consists of applying a pattern or a short series of patterns of input signals, until the device responds with a certain predetermined pattern of output signals. When this pattern has been received, the device is in a known state or homed. However, if the device fails to home because of a defect, the homing pattern would be applied continuously until a fail safe timer in the circuit tester shuts down the hardware. The fail safe timer is designed to prevent the tester from applying a set of patterns indefinitely and is usually set for the maximum possible test time for the entire test sequence to be applied. This could be long after upstream devices have been damaged. Third, the drivers used in the prior art have no provision for the control of overshoot which increases the risk of CMOS "latch up". All of these problems and more are resolved by the methods and apparatus to be described below.